Readers will acknowledge the well-known title Claude Elwood Shannon, extensively famend because the “father of data idea*”* and originator of many discoveries and innovations. Amongst these is a sublime and pioneering (First revealed in 1948!) design thought for a DAC referred to as the Shannon Decoder (SD) sketched in **Determine 1** (illustration modified from the *Knowledge Conversion Handbook © 2005 Analog Units*).

**Determine 1 **The Shannon decoder DAC.

In operation, the incoming serial (LSB-first) bit string controls change **S **so {that a} **1** bit provides a unit of cost to capacitor **C** whereas a **0** leaves it unchanged. Bits (altogether 4 on this easy instance) arrive at time intervals **T**. Thus, on the finish of **4T**, the ultimate voltage **V** collected on **C** represents the numeric content material of the string. The brilliantly easy (due to Shannon’s genius) trick that makes **V **proportional to the binary quantity **N **represented by the string is

**RC = T/Ln(2)**. This causes precisely half the collected voltage on **C **to discharge throughout every interval **T**, offering the binary bit weights vital for proper digital to analog conversion. The S&H then captures the ultimate outcome current on **C** at **4T**. And that’s it. We’ve accomplished a 4 bit DAC conversion in simply 4 bit instances utilizing nothing however a change, single stage RC, and S&H.

**Determine 2** suggests what an 8-bit SD would possibly seem like utilizing gadgets which have come alongside since 1948. Notice that it intently resembles a fundamental PWM DAC, consisting solely of a typical general-purpose output bit **D** and single-stage RC **(R + Ron)C = T/Ln(2)**. The **Ron** time period gives correction for ON resistance of the output port, usually 20Ω to 200Ω. We’ll see later why **Ron** issues. Assuming an instance 8 bit serial string = 10101011 = 171, **T**=10µs, **C**=0.0015µF, **Ron** =120Ω, **R**=9.53kΩ, and Vref = 5V logic provide, **Analog Out = 171/256 * 5V = 3.34V**.

**Determine 2 **A contemporary Shannon decoder implementation.

The required S&H operate is offered without charge by merely tri-stating **D** after **Analog Out** has been collected, permitting capacitor **C **to carry the ultimate voltage and thus be its personal S&H.

Beforehand I claimed the SD is a quicker different to PWM. Nicely, is it? An 8-bit PWM has a fundamental interval of 256 clock cycles, and with a view to suppress ripple to LSB ranges, the RC filter time fixed must equal ~64 PWM intervals, and can want an additional Ln(256) = 5.5 time constants to settle to 1 LSB. This provides as much as a complete PWM DAC conversion time of 256 *64*5.5 = 90,112 clock cycles to transform, filter, and settle to a ultimate 8-bit worth.

In the meantime, the 8-bit SD does all that in solely 8 **T **cycles, apparently yielding an SD vs PWM pace ratio of 90,112/8 = 11,264 to 1, performed with the identical elements rely as fundamental PWM!

However is that this actually a good comparability? Nicely, not solely.

To begin with, concerning pace, a PWM clock cycle will usually be generated in devoted on-chip counter-timer {hardware}, whereas the SD bit-shifting and ultimate tri-stating of the output port bit will possible want some software program interplay. This distinction is more likely to make the SD bit fee slower than the PWM clock. Maybe 10x slower. Due to this fact, a extra real looking estimate of the SD versus PWM pace ratio would in all probability be nearer to 1,100-to-1 than 11,000-to-1.

Secondly, concerning elements rely, there’s this consideration: Whereas PWM repeatedly and robotically refreshes its output, the essential SD as proven in **Determine 2** doesn’t. Each few milliseconds it’s vital for Determine 2 to run via a conversion cycle to refresh **C**’s cost, counteract voltage droop, and preserve a steady output. In fact, throughout these conversions **Analog Out **will likely be something *however* steady, creating what the load will see as a momentary output glitch.

Some masses will tolerate this periodic disturbance, however many is not going to. Avoiding the glitch is feasible, however to take action, elements rely should enhance. **Determine 3** suggests one potential resolution:

**Determine 3 **Supplementary PWM to stop SD output droop.

Supplementing the pace of the SD with a “sustainer” PWM set to the identical output voltage because the SD to carry the identical capacitor cost that was initially (shortly) set by the SD.

This resolution remains to be lower than good as a result of the big ratio between the SD and PWM time constants implies a equally massive ratio between R1 and R2, imposing a excessive resistance for R2 to get enough ripple suppression and therefore, a really restricted steady-state drive functionality for **Analog Out. **And naturally, there’s nonetheless an output glitch every time an SD conversion sequence units a brand new output voltage.

**Determine 4** reveals an entire treatment for these issues by implementing two S&H conversion/maintain capacitors that toggle *by way of* U1c in order that one gives the S&H operate (C0/1 as X/Y Choose = 0/1) and a relentless output voltage whereas the opposite performs the following DAC conversion *by way of* U1a and U1b. Whereupon they change roles, yada-yada and so forth, and so forth.

**Determine 4 **The toggling SD.

An extra function of Determine 4’s topology is its means to simply accept reference voltage inputs (**+Vref**, **-Vref**) which might be unbiased of logic provide and floor. This permits for higher DAC accuracy than counting on the (usually restricted) stability of logic energy provides, and, if **-Vref** is adverse, a bipolar (**-Vref** to **+Vref**) output span.

And it nonetheless wants simply 4 elements.

The SD has inherently programmable decision. Any size bit string (6, 10, 12, and so forth.) may be accommodated with none circuitry modification. Furthermore, as a result of the SD conversion time is linearly proportional to bit string size (**n**) whereas PWM conversion time is exponentially proportional to **2 ^{n}**, the SD’s pace benefit solely will get higher as string size grows.

SD precision relies on an correct match between RC time fixed and bit interval T/Ln(2). Variations between these two numbers will trigger bit weights to vary from the proper 2.0, and monotonicity and differential linearity to consequently endure. Use of precision steel movie resistors and nil tempco C0G or NPO capacitors is subsequently prompt, in addition to correction of **R **for the impedance (**Ron**) of switching components in SD sign paths, as beforehand talked about.

**Determine 5** reveals the impact on the conversion results of RC time fixed errors from 0% (**RC =** **1.44269 T**) to 10% (**RC = 1.58696 T**).

**Determine 5 **Impact of 0% to 10% RC error.

*Stephen Woodward’s relationship with *EDN’s* DI column goes again fairly a methods. In all, a complete of 64 submissions have been accepted since his first contribution was revealed in 1974.*

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