With the proliferation of 5G networks, cloud computing, Web of Issues (IoT) and virtualization, IT infrastructure is driving the demand for high-performance computing servers.
Every new server technology requires greater computing energy and effectivity, whereas additionally growing energy necessities. One of many key facets in guaranteeing that servers meet market calls for is to know the impact that the microprocessor’s energy provide has on each the dynamic response and effectivity of the server as a complete. That allows engineers to configure the ability provide for optimum efficiency.
Server purposes are particularly demanding relating to transient response necessities. With a view to meet these necessities, designers can implement load-line management, which is typically additionally known as energetic voltage positioning (AVP).
Understanding DC load-line design
Load line (LL) management refers to a modification of the voltage management loop the place the buck converter’s output voltage (VOUT) is adjustable primarily based on the load present. In different phrases, VOUT is now not fixed for all load values, and as an alternative adjustments in accordance with the ability demand. The adjusted output voltage might be calculated utilizing Equation 1:
VOUT = VOUT(NOM) – IOUT × RLL           (1)
The place VOUT(NOM) is the utmost VOUT when there is no such thing as a load linked to the ability provide, IOUT is the load present, and RLL is the equal load-line impedance (in Ω).
Determine 1 reveals how implementing load-line regulation degrades the DC load regulation (denoted with the blue line), inflicting VOUT to slope down as the present will increase, in comparison with the normal method that fixes VOUT for all hundreds (denoted with the inexperienced line). Notice that the voltage slope created by the load line should nonetheless be designed to fulfill the VOUT necessities for powering microprocessors. Which means that VOUT should fall inside specified voltage limits—VMAX and VMIN—for your complete output present vary.
Determine 1 The graph reveals VOUT with DC load line vs. the fastened VOUT technique. Supply: Monolithic Energy Techniques (MPS)
The primary purpose to implement load-line regulation is to decrease the voltage when the load present could be very massive, and thereby cut back energy consumption and dissipation loss. Whereas this can be a continuously mentioned profit, one other benefit of implementing load-line management is the way it improves the server’s dynamic response.
Energy provides in server purposes usually should assist massive load transients. It’s because energy provides in server purposes should energy hundreds corresponding to storage gadgets and CPUs, whose energy necessities fluctuate in accordance with the duty(s) they’re executing. For instance, it’s not unusual for a server energy provide to ship present steps properly above 100 A.
Determine 2 reveals an influence provide earlier than and after implementing the load line. Because of the present step, the ability provide with no load line—denoted with the purple line—experiences massive overshoots and undershoots throughout load transients. If these peaks exceed the utmost or minimal voltage limits, this will trigger the load to interrupt down and stop functioning. By steadily adjusting VOUT with the implementation of a load line—denoted with the blue line—these peaks might be eradicated and the transient response is improved.
Determine 2 The facility provide comparability earlier than and after implementing the load line highlights results on transient response. Supply: Monolithic Energy Techniques (MPS)
Whereas load line improves server efficiency and effectivity, the load-line configuration should be very correct, because the converter should at all times function throughout the set voltage limits. Most communication requirements specify ideally suited load-line values, however these values could should be tweaked as a consequence of completely different board supplies and layouts. In any other case, the load line could push the voltage beneath the minimal necessities when working at excessive energy (Determine 3).
Determine 3 Here’s a view of errors brought on by suboptimal load-line configurations. Supply: Monolithic Energy Techniques (MPS)
Lowering output capacitance with DC load line
To display the advantages of load line management, a common instance was created with typical processor specs for an influence rail. The enter voltage (VIN) was set to 12 V, the output present (ITDC) was 220 A, and the output voltage (VOUT) was 1.8 V—all of that are generic values for a voltage rail in server purposes. Desk 1 reveals the specs.
Desk 1 Energy rail specs. Supply: Monolithic Energy Techniques (MPS)
Desk 2 reveals the take a look at situations corresponding to output capacitance (COUT), switching frequency (fSW), and the variety of phases (NPHASE).
Desk 2 Check parameters. Supply: Monolithic Energy Techniques (MPS)
A dual-loop, digital, multi-phase controller—MP2965—was used to implement this instance, because it helps load-line configuration and might be configured for as much as 7-phase operation. The PMBus-configurable load line requires a droop resistor (RDROOP) to be linked between the VDIFF and VFB pins, in addition to inside register configurations (Determine 4)
Determine 4 Right here is how the controller-based load-line inside construction appears like. Supply: Monolithic Energy Techniques (MPS)
First, a designer should set up the impact of the load line by observing the voltage regulation when the converter doesn’t use a load line. A 160-A present step was utilized to the MP2965 multi-phase controller to emulate a CPU load. Determine 5 reveals the converter’s response with no DC load line. Notice the big VOUT spikes that happen throughout the present transients. This implies there’s a voltage variation of 205 mV, which is barely contained in the specs proven in Desk 1.
Determine 5 The converter response to a present step is with out DC load line. Supply: Monolithic Energy Techniques (MPS)
Utilizing Equation 1, a load line of 0.67 mΩ was designed to fulfill the minimal VOUT specification, estimated with Equation 2.
VOUT = VID – IOUT × RLL → RLL = VOUT(NOM) – VOUT(MIN)/IOUT(MAX) = 108 mV/160 A = 0.675 mΩ          (2)
Determine 6 reveals the ensuing transient response after implementing a DC load line.
Determine 6 The converter response to a present step is with DC load line. Supply: Monolithic Energy Techniques (MPS)
By implementing a DC load line, VOUT stays properly throughout the voltage vary laid out in Desk 1, with a voltage margin of about 50% of the permitted vary. This elevated voltage margin additionally signifies that sure design constraints might be loosened, such because the output capacitance, which is among the key components used to scale back the peaks in output voltage. As laid out in Desk 2, the voltage responses proven in Determine 5 and Determine 6 discuss with a complete output capacitance of 4.7 mF, comprised of 60 22-μF MLCC capacitors positioned near the CPU load, together with a number of aluminum electrolytic capacitors.
The MLCC capacitors filter out the high-frequency parts of the present transient response, whereas the aluminum electrolytic capacitors filter out the low-frequency parts. These aluminum capacitors, known as bulk capacitors, are specifically designed with a really low equal sequence resistance (ESR), that means that they’re usually the costliest capacitors within the circuit. In consequence, having fewer bulk capacitors reduces the general price and BOM.
Since implementing the DC load line already reduces the transient peaks, bulk capacitance turns into much less essential for transient response and the majority capacitor’s ESR necessities are additionally decreased. Due to this fact, a number of the bulk capacitors might be eliminated with out having a major impact on the circuit’s transient response. Determine 7 reveals the outcomes after decreasing the majority capacitance by 50% (from 6 x 470 µF to three x 470 µF).
Determine 7 The converter response to present step is with DC load line and fewer bulk capacitors. Supply: Monolithic Energy Techniques (MPS)
To extend the voltage margin for each optimistic and detrimental spikes, a 40-mV DC offset was added to VOUT. This locations VOUT close to the middle of the voltage vary outlined by the specs.
Though there are fewer bulk capacitors, there is no such thing as a seen change within the energy provide’s transient response. Nonetheless, this nonetheless gives the benefit of decreased price and board area.
A further good thing about load line is the decreased CPU energy dissipation. When VOUT is about to 1.8 V at 160 A, the load energy is 288 W. By implementing the DC load line and reducing VOUT to 1.725 at most present, the load energy from Determine 7 is 276 W, which represents a internet energy saving of 12 W.
Advantages of load-line management
Server and computing purposes require energy provides that may deal with massive, sudden shifts in present whereas assembly strict VOUT regulation necessities.
Utilizing a digital controller to implement a PMBus-configurable load line, this text has demonstrated the load-line management advantages corresponding to improved effectivity and improved energy provide transient response efficiency. The article additionally defined how implementing a DC load line reduces the minimal required bulk capacitance, permitting designers to scale back total price and decrease board area whereas nonetheless assembly specs for server purposes.
Marisol Carbrera is senior purposes engineer at Monolithic Energy Techniques.
Tomas Hudson is purposes engineer at Monolithic Energy Techniques.
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